Field of the Invention
The present invention relates to an apparatus and a method for determining intra prediction mode when intra prediction encoding is performed on an image, and a recording medium.
Description of the Related Art
As a method for encoding moving images, H.264/MPEG-4 AVC (hereinafter simply referred to as “H.264”) is generally used. Furthermore, as a successor method of H.264, activity of international standardization of an encoding method of higher efficiency is started and JCT-VC (Joint Collaborative Team on Video Coding) is established by ISO/IEC and ITU-T. In the JCT-VC, standardization of a high efficiency video coding method (hereinafter referred to as “HEVC”) is promoted (refer to ITU-T H.265(04/2013) High efficiency video coding).
In the HEVC, intra prediction encoding in which a prediction residual (prediction error) generated by performing intra-frame prediction (hereinafter referred to as “intra prediction”) using correlations among pixels in a frame (image) is encoded is employed in order to improve encoding efficiency. Furthermore, in the HEVC, as a size of a prediction block which is a unit of intra prediction (hereinafter referred to as a “prediction block size”), one of five types of sizes including 64×64 pixels, 32×32 pixels, 16×16 pixels, 8×8 pixels, and 4×4 pixels is employed. Note that the term “64×64 pixels” represents a block having pixels in a matrix of 64 rows and 64 columns, and in this embodiment, this block is referred to as “64×64 pixels” hereinafter. The same is true of blocks having the other numbers of pixels. Furthermore, in the HEVC, encoding by combining a plurality of block sizes has been discussed. In an example of FIG. 8, intra prediction of a block size of 4×4 pixels and intra prediction of a block size of 8×8 pixels are combined with each other. In this way, in the HEVC, intra prediction may be performed on a single encoding block by a plurality of prediction block sizes. The pixels are constituted by samples of luminance components and chrominance components. In a case of 64×64 pixels in the YUV420 format, the pixels are constituted by 64×64 samples of luminance components and two 32×32 samples of chrominance components. Here, for sake of simplicity of description, the term “pixel” and the term “sample” are described as synonymous with each other. Specifically, the term “pixel” may be replaced by the term “sample” in the description hereinafter.
Furthermore, the number of prediction modes of the prediction block sizes in the HEVC is 4 in the block size of 64×64 pixels, 35 in the block sizes of 32×32 pixels, 16×16 pixels, and 8×8 pixels, and 18 in the block size of 4×4 pixels (refer to FIG. 20A). Furthermore, modes (Associated names) associated with prediction modes 0 to 34 (intra prediction modes) are illustrated in FIG. 20B. In FIG. 20B, an Intra_Angular mode is associated to the prediction modes 4 to 33, and a method for generating a prediction image is shared by the prediction modes 4 to 33.
When the intra prediction is performed using such an encoding method, a large prediction error is generated, and therefore, encoding efficiency is lowered unless an appropriate combination between one of a plurality of available prediction modes and one of the plurality of block sizes is selected. Therefore, all available prediction modes and all available prediction block sizes are examined and an appropriate one of the prediction modes and an appropriate one of the prediction block size are selected.
Furthermore, in a case where all the prediction modes and all the prediction block sizes are to be examined, if the plurality of block sizes are examined in parallel, a processing time required for encoding may be reduced. However, special hardware is required for the examinations of the block sizes and the prediction modes, and accordingly, a circuit size is increased. As a technique for suppressing the increase of a circuit size, in general, techniques disclosed in Japanese Patent Laid-Open Nos. 2011-151655 and 2007-266679 have been proposed. The technique employed in Japanese Patent Laid-Open No. 2011-151655 employs a configuration in which a single intra prediction unit may determine intra prediction modes of a plurality of macro block sizes, and reduction of a circuit size of a moving-image encoding unit is realized. In Japanese Patent Laid-Open No. 2007-266679, a circuit size is reduced by performing examinations of a block of 16×16 pixels in various intra prediction modes using a prediction unit which performs prediction on a block of 4×4 pixels while the block of 4×4 pixels is locally decoded.
However, in Japanese Patent Laid-Open No. 2011-151655, the plurality of encoding blocks are successively examined in various prediction modes using the single intra prediction unit. Therefore, when an encoding method having a large number of available prediction modes and a large number of available types of prediction block size, such as the HEVC, is employed, the following problem arises. Specifically, in this case, a processing time required for a determination of a prediction mode and a prediction block size for one encoding block is increased, and as a result, processing performance of an entire encoding apparatus is degraded.
Similarly, when the HEVC is employed in Japanese Patent Laid-Open No. 2007-266679, the number of prediction modes to be examined for each prediction block size is increased, and therefore, a period of time required for a determination of a prediction mode for one prediction block is increased. Furthermore, when an encoding block constituted by a plurality of prediction block sizes as illustrated in FIG. 8 is encoded in Japanese Patent Laid-Open No. 2007-266679, a processing time required for the local decoding and a processing time required for generation of a prediction image are considerably changed depending on a prediction block size to be processed. Therefore, a period of time in which an incorporated calculation unit is stopped is generated, and accordingly, the calculation unit is not efficiently used.
On the basis of the problems above, the present invention provides, in a process of examining a plurality of prediction block sizes in various intra prediction modes, a determination of an appropriate prediction block size and an appropriate prediction mode at high speed while increase of a circuit size is suppressed.